Name
Abstract | ||
|---|---|---|
We propose a new DSP block for use in modern high-performance FPGAs. Current DSP blocks contain fixed-bitwidth multipliers that can be combined efficiently to form larger multipliers. Our approach is similar, but includes a bypass layer following the partial product generator that exposes the compressor tree used for partial product reduction directly to the user. As a consequence, the proposed DSP block can accelerate multi-input addition operations in addition to multiplication. To increase the flexibility of the device, the partial product reduction tree used within our DSP block uses a fixed-function compression logic along with a field programmable compressor tree (FPCT), the latter of which is user-configurable to meet the needs of the application at hand. Multi-input addition operations can be mapped directly onto the FPCT without compromising any of the other functionality of the DSP block. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/FPT.2009.5377638 | Sydney, NSW |
Keywords | Field | DocType |
digital signal processing chips,field programmable gate arrays,DSP block,FPGA arithmetic performance,field programmable compressor tree,fixed-bitwidth multipliers,fixed-function compression logic,multi-input addition operations,partial product generator | Partial product,Digital signal processing,Adder,Computer science,Parallel computing,Field-programmable gate array,Gas compressor,Multiplication,Computer hardware,Partial product reduction,Embedded system | Conference |
ISBN | Citations | PageRank |
978-1-4244-4377-2 | 3 | 0.43 |
References | Authors | |
21 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Parandeh-Afshar, H. | 1 | 3 | 0.43 |
| Cevrero, A. | 2 | 3 | 0.43 |
| Athanasopoulos, P. | 3 | 3 | 0.43 |
| Philip Brisk | 4 | 786 | 60.63 |