Name
Abstract | ||
|---|---|---|
We begin this survey of the system bus interface protocols common to the PowerPC 601, 603, and 604 microprocessors by discussing the basic address and data transfer mechanisms, classes of bus operations, and hardware-enforced coherency mechanisms. Next we focus on the microprocessor design solutions, from the specific cache organizations, through the memory buffering, to the bus interfaces. |
Year | DOI | Venue |
|---|---|---|
1994 | 10.1109/MM.1994.363068 | IEEE Micro |
Keywords | Field | DocType |
workstations,hardware,microcomputers,file servers | File server,Computer science,Parallel computing,Workstation,Processor scheduling,PowerPC,Embedded system | Journal |
Volume | Issue | ISSN |
14 | 5 | 0272-1732 |
Citations | PageRank | References |
6 | 2.65 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Allen, M.S. | 1 | 6 | 2.65 |
| Alexander, M. | 2 | 6 | 2.65 |
| Wright, C. | 3 | 6 | 2.65 |
| Chang, J. | 4 | 6 | 2.65 |