Name
Abstract | ||
|---|---|---|
This paper describes an LSI that was developed for wide application in digital video signal processing. The newly developed LSI consists of two independent 12-bit full adders/subtracters and a variable delay unit. The minimum arithmetic operation cycle time is 67 nsec and power dissipation is 250 mW. The LSI is packaged in a 135 pin RIT package. It has rather simple structure, but has very powerful applications in real time video signal processing. The application of this LSI for TV conference CODEC is also presented as an example. |
Year | DOI | Venue |
|---|---|---|
1986 | 10.1109/ICASSP.1986.1169149 | Acoustics, Speech, and Signal Processing, IEEE International Conference ICASSP '86. |
Keywords | DocType | Volume |
signal processing,power dissipation,codecs,real time,adders,cycle time,circuits,arithmetic,tv | Conference | 11 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| shinichi maki | 1 | 0 | 0.34 |
| kiichi matsuda | 2 | 0 | 0.34 |
| toshitaka tsuda | 3 | 0 | 0.34 |
| hiroshi fukui | 4 | 0 | 0.34 |
| Hirohisa Gambe | 5 | 1 | 0.72 |