Name
Title | ||
|---|---|---|
Modeling of FPGA local/global interconnect resources and derivation of minimal test configurations |
Abstract | ||
|---|---|---|
This paper addresses the issues of automating the derivation of test configurations (TCs) for both local and global interconnect of SRAM-based FPGAs. We model FPGA interconnect and their test requirements using adjacency graphs and obtain the minimal or near minimal TO by solving the graph coloring problem, using a modified greedy algorithm. We apply the proposed modeling and TC derivation method to the Xilinx XC4000 FPGA. A set of minimal TCs was derived automatically. The proposed method is applicable to FPGAs of various interconnect structures and sizes, and supports distinctive test logic. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/DFTVS.2002.1173525 | DFT |
Keywords | Field | DocType |
automatic testing,field programmable gate arrays,graph colouring,integrated circuit interconnections,logic testing,network routing,SRAM-based FPGAs,Xilinx XC4000,adjacency graphs,distinctive test logic,graph coloring problem,interconnect sizes,interconnect structures,local/global interconnect resources,minimal test configurations,modified greedy algorithm | Adjacency list,Computer science,System testing,Parallel computing,Field-programmable gate array,Application-specific integrated circuit,Static random-access memory,Greedy algorithm,Electronic engineering,Interconnection,Graph coloring | Conference |
ISSN | ISBN | Citations |
1550-5774 | 0-7695-1831-1 | 6 |
PageRank | References | Authors |
0.72 | 11 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xiaoling Sun | 1 | 86 | 10.89 |
| Alimohammad, A. | 2 | 6 | 0.72 |
| Pieter M. Trouborst | 3 | 6 | 0.72 |