Name
Abstract | ||
|---|---|---|
The paper describes a VLSI architecture designed to reconstruct a subband-encoded video stream. This architecture differs from previous designs in its low power operation. The chip operates at a maximum 20 MHz with a 1.5 V supply and can process up to 10 M color (YUV) pixels/sec while dissipating only 16 mW. The low power consumption is achieved through efficient algorithm-to-hardware mapping, a low-complexity subband filter, minimal memory accesses, a reduced supply voltage, and elimination of external memory support. A single chip will support color images up to 352 pixels wide, while multiple chip configurations can achieve any desired display resolution |
Year | DOI | Venue |
|---|---|---|
1994 | 10.1109/ICASSP.1994.389634 | Acoustics, Speech, and Signal Processing, 1994. ICASSP-94., 1994 IEEE International Conference |
Keywords | Field | DocType |
VLSI,decoding,digital signal processing chips,image reconstruction,power consumption,video equipment,video signal processing,1.5 V,16 mW,20 MHz,VLSI architecture,algorithm-to-hardware mapping,display resolution,external memory support,low power subband video decoder architecture,low-complexity subband filter,minimal memory accesses,multiple chip configuration,power consumption,reduced supply voltage,single chip configuration,subband-encoded video stream | Computer science,Real-time computing,Artificial intelligence,Computer hardware,Very-large-scale integration,Video decoder,Display resolution,Pattern recognition,Voltage,Chip,Pixel,Decoding methods,Auxiliary memory | Conference |
Volume | ISSN | ISBN |
ii | 1520-6149 | 0-7803-1775-0 |
Citations | PageRank | References |
8 | 35.76 | 2 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Gordon, B.M. | 1 | 8 | 35.76 |
| Meng, T.H.Y. | 2 | 8 | 35.76 |