Paper Info
Title
Genetic algorithm based test scheduling and test access mechanism design for system-on-chips
Abstract
We present a genetic algorithm (GA) based approach to solve the problems of test scheduling and test access mechanism partition for system on chips. The approach provides highly optimal results, comparable to the integer linear programming formulation of similar problems within very small CPU times. The results of GA based approach are shown to be superior to the heuristic approaches proposed in the literature.
Year
DOI
Venue
2003
10.1109/ICVD.2003.1183160
VLSI Design
Keywords
Field
DocType
automatic testing,genetic algorithms,integrated circuit testing,scheduling,system-on-chip,CPU times,genetic algorithm,heuristic approaches,system-on-chips,test access mechanism,test scheduling
Fixed-priority pre-emptive scheduling,Heuristic,Fair-share scheduling,Computer science,Parallel computing,Flow shop scheduling,Two-level scheduling,Real-time computing,Rate-monotonic scheduling,Genetic algorithm,Round-robin scheduling
Conference
ISSN
ISBN
Citations 
1063-9667
0-7695-1868-0
5
PageRank 
References 
Authors
0.42
11
2
Name
Order
Citations
PageRank
Santanu Chattopadhyay1121.21
K. Sudarsana Reddy250.42