Name
Abstract | ||
|---|---|---|
The BSP (bulk synchronous parallel) architecture incorporates a scalable and transparent communication model. The task-level synchronisation mechanism of the machine, however, is not transparent to the user and can be inefficient when applied to the co-ordination of irregular parallelism. This article presents a discussion of an alternative memory-level scheme which offers the prospect of achieving both efficient and transparent synchronisation. The scheme, based on a discrete-event simulation paradigm, supports a sequential style of programming and, coupled with the BSP communication model, leads to the emergence of a virtual von Neumann parallel computer.<> |
Year | DOI | Venue |
|---|---|---|
1994 | 10.1049/cce:19950307 | Parallel Architectures and Languages Europe |
Keywords | Field | DocType |
discrete event simulation,parallel architectures,parallel machines,programming,synchronisation,virtual machines,BSP communication model,bulk synchronous parallel architecture,discrete event simulation,irregular parallelism coordination,memory-level scheme,scalable communication model,sequential programming style,task-level synchronisation mechanism,transparent communication model,transparent synchronisation,virtual von Neumann parallel computer | Synchronization,Architecture,Computer science,Parallel computing,Models of communication,Bulk synchronous parallel,Von Neumann architecture,Distributed computing,Discrete event simulation,Scalability | Conference |
Volume | Issue | ISSN |
6 | 3 | 0956-3385 |
ISBN | Citations | PageRank |
3-540-58184-7 | 3 | 0.78 |
References | Authors | |
9 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Nasser Kalantery | 1 | 16 | 6.03 |
| S.C Winter | 2 | 4 | 2.82 |
| Derek R. Wilson | 3 | 5 | 2.24 |