Name
Abstract | ||
|---|---|---|
Relative timing (RT) is introduced as a method for asynchronous design. Timing requirements of a circuit are made explicit using relative timing. Timing can be directly added, removed, and optimized using this style. RT synthesis and verification are demonstrated on three example circuits, facilitating transformations from speed-independent circuits to burst-mode and pulse-mode circuits. Relative timing enables improved performance, area, power, and functional testability of up to a factor of 3/spl times/ in all three cases. This method is the foundation of optimized timed circuit designs used in an industrial test chip, and may be formalized and automated. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1109/TVLSI.2002.801606 | VLSI) Systems, IEEE Transactions |
Keywords | Field | DocType |
asynchronous circuits,formal verification,graph theory,integrated circuit design,integrated logic circuits,logic design,low-power electronics,timing,RT synthesis,RT verification,asynchronous design,burst-mode circuits,dynamic logic circuit,functional testability,low-power design,performance tradeoffs,pulse-mode circuits,relative timing method | Testability,Logic synthesis,Asynchronous communication,Computer science,Real-time computing,Electronic engineering,Integrated circuit design,Electronic design automation,Static timing analysis,Electronic circuit,Formal verification | Journal |
Volume | Issue | ISSN |
11 | 1 | 1063-8210 |
Citations | PageRank | References |
37 | 2.13 | 16 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ken S. Stevens | 1 | 37 | 2.13 |
| Ran Ginosar | 2 | 1410 | 135.61 |
| Shai Rotem | 3 | 102 | 7.33 |