Paper Info
Title
On the implementation of an efficient performance driven generator for conditional-sum-adders
Abstract
The authors present data structures and an efficient algorithm realizing efficient performance driven generation of integer adders. The generator is parameterized in n, the operands' bitlength, and tn , the delay of the addition. It outputs an area minimal n-bit adder of the conditional-sum type with delay ⩽tn, if such a circuit exists
Year
DOI
Venue
1993
10.1109/EURDAC.1993.410668
EURO-DAC
Keywords
Field
DocType
vlsi,adders,data structures,integrated logic circuits,logic cad,logic design,optimisation,algorithm,area minimal n-bit adder,conditional-sum,conditional-sum-adders,delay,dynamic programming,efficient performance driven generator,integer adders,point location,data structure,circuits,very large scale integration,concurrent computing
Logic synthesis,Integer,Data structure,Parameterized complexity,Adder,Computer science,Operand,Theoretical computer science,Logic family,Very-large-scale integration
Conference
ISBN
Citations 
PageRank 
0-8186-4350-1
1
0.36
References 
Authors
7
3
Name
Order
Citations
PageRank
B. Becker141136.80
Rolf Drechsler23707351.36
P. Molitor321118.50