Abstract | ||
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A low-power 435-MHz single-ended low-noise amplifier was implemented in a 0.35-μm silicon on insulator (SOI) CMOS technology. The SOI CMOS LNA has a simulated noise figure of 0.6 dB, input 1-dB compression point of -12.5 dBm, input third-order intercept point of -5 dBm, and small-signal gain of 22 dB. Total power dissipation is 10 mW from a 2.5-V supply. LNA chip area is 1.4 mm × 0.58 mm. Due to high-resistivity silicon substrate and buried oxide isolation, SOI CMOS technology offers significant performance improvements for mixed-signal VLSI and RF/Microwave integrated circuits. |
Year | DOI | Venue |
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2003 | 10.1109/ISCAS.2003.1205558 | Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium |
Keywords | DocType | Volume |
cmos analogue integrated circuits,uhf amplifiers,uhf integrated circuits,integrated circuit noise,low-power electronics,silicon-on-insulator,0.35 micron,0.6 db,10 mw,2.5 v,22 db,435 mhz,rf integrated circuit,soi cmos technology,si,buried oxide isolation,high-resistivity silicon substrate,input compression point,input third-order intercept point,low-power low-noise amplifier,mixed-signal vlsi,noise figure,power dissipation,small-signal gain,chip,low noise amplifier,cmos technology,very large scale integration,low power electronics,silicon on insulator,integrated circuit,gain | Conference | 1 |
ISBN | Citations | PageRank |
0-7803-7761-3 | 0 | 0.34 |
References | Authors | |
1 | 4 |
Name | Order | Citations | PageRank |
---|---|---|---|
Ertan Zencir | 1 | 5 | 2.39 |
Numan Sadi Dogan | 2 | 7 | 3.63 |
Ercument Arvas | 3 | 57 | 32.83 |
Mohammed Ketel | 4 | 13 | 6.84 |