Name
Abstract | ||
|---|---|---|
Rapid evaluation and design space exploration at the algo- rithmic level are important issues in the design cycle. In this paper we propose an original area vs delay estimation methodology that targets reconfigurable architectures. Two main steps compose the estimation flow: i) the structural es- timation which is technological independent and performs an automatic design space exploration and ii) the physical estimation which performs a technologic mapping to the tar- get reconfigurable architecture. Experiments conducted on Xilinx (XC4000, Virtex) and Altera (Flex10K, Apex) com- ponents for a 2D DWT and a speech coder lead to an aver- age error of about 10 % for temporal values and 18 % for area estimations. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1109/ISCAS.2003.1206381 | Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium |
Keywords | Field | DocType |
C language,circuit layout CAD,delay estimation,discrete wavelet transforms,field programmable gate arrays,integrated circuit layout,logic CAD,reconfigurable architectures,software prototyping,speech coding,2D DWT,Altera components,C program,Xilinx components,algorithmic level,area estimation methodology,automatic design space exploration,delay estimation methodology,design space exploration,fast prototyping,physical estimation,rapid evaluation,reconfigurable architectures,speech coder,structural estimation,technologic mapping | Integrated circuit layout,Computer architecture,Speech coding,Space technology,Computer science,High-level synthesis,Software prototyping,Field-programmable gate array,Electronic engineering,Virtex,Design space exploration | Conference |
Volume | ISBN | Citations |
5 | 0-7803-7761-3 | 13 |
PageRank | References | Authors |
0.80 | 1 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sebastien Bilavarn | 1 | 67 | 8.72 |
| Guy Gogniat | 2 | 517 | 53.11 |
| Jean-Luc Philippe | 3 | 61 | 6.49 |
| Lilian Bossuet | 4 | 333 | 36.10 |