Paper Info
Title
A class of random multiple bits in a byte error correcting and single byte error detecting (Stb/EC-SbED) codes
Abstract
Correcting multiple random bit errors that corrupt a single DRAM chip becomes very important in certain applications, such as semiconductor memories used in computer and communication systems, mobile systems, aircraft, and satellites. This is because, in these applications, the presence of strong electromagnetic waves in the environment or the bombardment of an energetic particle on a DRAM chip is highly likely to upset more than just one bit stored in that chip. On the other hand, entire chip failures are often presumed to be less likely events and, in most applications, detection of errors caused by single chip failures are preferred to correction due to check bit length considerations. Under this situation, codes capable of correcting random multiple bit errors that are confined to a single chip output and simultaneously detecting errors caused by single chip failures are attractive for application in high speed memory systems. This paper proposes a class of codes called Single t/b-error Correcting-Single b-bit byte Error Detecting (Stb/EC-SbED) codes which have the capability of correcting random t-bit errors occurring within a single b-bit byte and simultaneously indicating single b-bit byte errors. For the practical case where the chip data output is 8 bits, i.e., b = 8, the S38/EC-S8ED code proposed in this paper, for example, requires only 12 check bits at information length 64 bits. Furthermore, this S38/EC-S8ED code is capable of correcting errors caused by single subarray data faults, i.e., single 4-bit byte errors, as well. This paper also shows that perfect S(b-t)b/EC-SbED codes, i.e., perfect Stb/EC-SbED codes for the case where t = b - 1, do exist and provides a theorem to construct these codes.
Year
DOI
Venue
2003
10.1109/TC.2003.1214333
IEEE Transactions on Computers
Keywords
Field
DocType
DRAM chips,error correction,error correction codes,error detection,error detection codes,integrated circuit reliability,DRAM chip,byte error correcting codes,check bits,chip data output,electromagnetic waves,high speed memory systems,random multiple bit errors,semiconductor memories,single byte error detecting codes,single chip failures,single subarray data faults
Parity bit,Byte,Computer science,Parallel computing,Error detection and correction,Chip,Upset,Dram chip,High speed memory,Bit error rate
Journal
Volume
Issue
ISSN
52
7
0018-9340
Citations 
PageRank 
References 
19
2.39
6
Authors
2
Name
Order
Citations
PageRank
Ganesan Umanesan1305.92
Eiji Fujiwara218031.14