Name
Abstract | ||
|---|---|---|
Retiming is a very promising transformation of circuits which preserves functionality and improves performance. Its benefits are especially promising in automatic synthesis of circuits from higher-level descriptions. However, retiming has not been widely included in current design tools and methodologies. One of the main obstacles is the problem of finding an equivalent initial state for the retimed circuit. In this paper, we introduce a simple modification of the retiming algorithm of Leiserson and Saxe. The modified algorithm helps minimize the effort required to find equivalent initial states and reduces the chance that the network needs to be modified in order to find an equivalent initial state. This algorithm is the kernel of a new efficient retiming method, which searches for optimal retimings while preserving the initial state condition. The paper also presents an improved method to perform the initial state calculation |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1109/43.489105 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | DocType | Volume |
circuit CAD,circuit optimisation,logic CAD,sequential circuits,timing,automatic synthesis,circuit optimisation,circuit transformation,design tools,equivalent initial state,higher-level descriptions,optimal retimings,register relocation,retiming algorithm,sequential circuits | Journal | 15 |
Issue | ISSN | Citations |
3 | 0278-0070 | 36 |
PageRank | References | Authors |
2.08 | 10 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| G. Even | 1 | 100 | 7.19 |
| Spillinger, I.Y. | 2 | 36 | 2.08 |
| Stok, L. | 3 | 66 | 3.69 |