Name
Abstract | ||
|---|---|---|
Quiescent chip current (Iddq) has been known for many years, but its role has changed in just the past few years from a valuable means to screen for reliability to a demon threatening to derail the industry's phenomenal march of VLSI performance advances. Iddq originates with a phenomenon that is well-understood at the level of an individual transistor. However, at the chip level, both inter-chip and intra-chip process skew introduce wide and unexpected variation in Iddq. Despite these effects, meaningful predictions of Iddq can still be made at different points in the chip design cycle. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1109/CICC.2003.1249474 | custom integrated circuits conference |
Keywords | DocType | ISBN |
vlsi,integrated circuit design,integrated circuit modelling,leakage currents,iddq estimation,iddq variation,early chip design decisions,inter-chip process skew,intra-chip process skew,leakage power,quiescent chip current,reliability screening,technology design decisions,chip | Conference | 0-7803-7842-3 |
Citations | PageRank | References |
3 | 0.78 | 2 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hook, T. | 1 | 3 | 0.78 |
| Wissel, L. | 2 | 3 | 0.78 |
| Mazgaj, D. | 3 | 3 | 0.78 |