Title
Detecting and locating faults in VLSI implementations of the Advanced Encryption Standard
Abstract
Concurrent fault detection for hardware implementations of the Advanced Encryption Standard (AES) may provide protection against random faults, and against an attacker who may maliciously inject faults in order to find the encryption secret key. We have recently developed such a scheme which is based on the parity code. In this paper we prove that the parity-based code detects all odd-order faults and allows the location of the most single transient and permanent faults.
Year
DOI
Venue
2003
10.1109/DFTVS.2003.1250101
DFT
Keywords
Field
DocType
VLSI,cryptography,fault location,integrated circuit modelling,integrated circuit reliability,integrated circuit testing,parity check codes,telecommunication security,telecommunication standards,AES,Advanced Encryption Standard,VLSI implementations,concurrent fault detection,encryption secret key,fault injection,fault location,hardware implementations,odd-order faults,parity code,permanent faults,random fault protection,single transient faults
Stuck-at fault,Hardware implementations,Computer science,Fault detection and isolation,Cryptography,Advanced Encryption Standard,Encryption,Real-time computing,Electronic engineering,Vlsi implementations,Very-large-scale integration
Conference
ISSN
ISBN
Citations 
1550-5774
0-7695-2042-1
12
PageRank 
References 
Authors
1.03
7
4
Name
Order
Citations
PageRank
Guido Marco Bertoni118013.79
Breveglieri, L.218716.43
Israel Koren31579175.07
P. Maistri420011.98