Name
Abstract | ||
|---|---|---|
In this paper, a novel compression/decompression test approach for system-on-a-chip (SoC) test using an embedded FPGA core is presented. The approach, employing Huffman coding, achieves test data volume and test application time reduction. The approach makes effective use of the embedded FPGA core such that the implementation is more efficient than that of the embedded processor-based approach. Due to the reconfigurable capability of FPGAs, the implementation of this approach has zero hardware overhead and higher flexibility in comparison with the general hardware-based implementation. Since the application with the FPGA has common problems of low speed and high power consumption, we demonstrate how to apply a CAM-based (content-addressable-memory) decompression architecture and low-power scan test vectors to overcome the difficulties. It is proven that the proposed approach is efficient from the experimental results. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1109/DFTVS.2003.1250149 | DFT |
Keywords | Field | DocType |
Huffman codes,automatic test pattern generation,boundary scan testing,content-addressable storage,data compression,field programmable gate arrays,logic design,logic testing,system-on-chip,ATPG,CAM-based decompression architecture,FPGA decoder,Huffman coding,SoC testing,content-addressable-memory,data compression,embedded FPGA core,lossless compression algorithms,low-power scan test vectors,scan testing,system-on-a-chip,test application time reduction,test data decompression,test data volume reduction | Logic synthesis,Automatic test pattern generation,System on a chip,Computer science,FPGA prototype,Field-programmable gate array,Electronic engineering,Huffman coding,Test data,Computer hardware,Data compression,Embedded system | Conference |
ISSN | ISBN | Citations |
1550-5774 | 0-7695-2042-1 | 8 |
PageRank | References | Authors |
0.54 | 9 | 2 |