Title
An integrated approach for improving cache behavior
Abstract
The widening gap between processor and memory speeds renders data locality optimization a very important issue in data-intensive embedded applications. Throughout the years hardware designers and compiler writers focused on optimizing data cache locality using intelligent cache management mechanisms and program-level transformations, respectively. Until now, there has not been significant research investigating the interaction between these optimizations. In this work, we investigate this interaction and propose a selective hardware/compiler strategy to optimize cache locality for integer, numerical (array-intensive), and mixed codes. In our framework, the role of the compiler is to identify program regions that can be optimized at compile time using loop and data transformations and to mark (at compile-time) the unoptimizable regions with special instructions that activate/deactivate a hardware optimization mechanism selectively at run-time. Our results show that our technique can improve program performance by as much as 60% with respect to the base configuration and 17% with respect to a non-selective hardware/compiler approach.
Year
DOI
Venue
2003
10.1109/DATE.2003.1253704
DATE
Keywords
Field
DocType
cache storage,embedded systems,hardware-software codesign,memory architecture,base configuration,cache behavior,cache locality,data locality optimization,data transformations,data-intensive embedded applications,loop transformations,optimization mechanism
Loop nest optimization,Computer architecture,Cache pollution,Computer science,Cache,Compiler correctness,Parallel computing,Loop optimization,Cache algorithms,Real-time computing,Compiler,Loop interchange
Conference
ISSN
ISBN
Citations 
1530-1591
0-7695-1870-2
1
PageRank 
References 
Authors
0.39
9
4
Name
Order
Citations
PageRank
Gokhan Memik110.39
Mahmut Kandemir210.39
Alok Choudhary320511.94
Ismail Kadayif410.39