Name
Abstract | ||
|---|---|---|
This paper analyses the impact of the power supply voltage on the logical behavior of resistive Bridging Fault. It is theoretically demonstrated that the interval of resistance corresponding to the appearance of a faulty value exponentially increases when the power supply decreases. Using the Parametric Model specifically developed for resistive bridging faults, results of parametric bridging faults simulations on benchmark circuits clearly show an improvement of about 40% when a lower-than-normal power supply is used. Moreover this bridging fault coverage improvement technique doesn't need any additional effort such as Design for Testability or specific Test Pattern Generation. |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1109/VTEST.1996.510877 | Princeton, NJ |
Keywords | Field | DocType |
VLSI,automatic testing,fault diagnosis,integrated circuit testing,logic testing,VLSI,benchmark circuits,bridging fault coverage,faulty value,logic circuits,parametric model,power supply control,resistance interval | Design for testing,Logic gate,Parametric model,Fault coverage,Computer science,Bridging fault,Resistive touchscreen,Bridging (networking),Real-time computing,Electronic engineering,Parametric statistics,Reliability engineering | Conference |
ISSN | ISBN | Citations |
1093-0167 | 0-8186-7304-4 | 23 |
PageRank | References | Authors |
1.21 | 12 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Renovell, M. | 1 | 23 | 1.21 |
| Huc, P. | 2 | 23 | 1.21 |
| Bertrand, Y. | 3 | 23 | 1.21 |