Name
Abstract | ||
|---|---|---|
This paper presents a jfloorplanner for datapath with the capability of re-allocating data storage for minimizing the interconnect area and critical path delay without altering the number of Functional units and the schedule. The tool has combined two novel approaches: 1 -A placement & Routing model to handle different architectural topologies (mux. and/ or bus based) suitable for FPGA's. 2 - An efJicient formulation for the biruling of register/lnterconnect & combined Floorplanning. The complexity of the architectural and jloorplanning model, and of the cost finction, have led us to the use of a stochastic optimization process. The running time of the whole process indicates the viability of the method. We show through various examples how the jloorplmner improves the area and critical path delay of the datapath compared to a plainjloorplannel: The improvement is about 20% for the critical path delay when this objective is a stringent constraint. |
Year | DOI | Venue |
|---|---|---|
1995 | 10.1109/ISCAS.1995.521446 | Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium |
Keywords | Field | DocType |
VLSI,circuit layout CAD,circuit optimisation,field programmable gate arrays,integrated circuit layout,logic CAD,network routing,FPGA,cost function,critical path delay,data storage reallocation,datapath optimization,floorplanner,interconnect area,placement/routing model,stochastic optimization process | Integrated circuit layout,Datapath,Stochastic optimization,Computer science,Parallel computing,Field-programmable gate array,Multiplexer,Electronic engineering,Network topology,Very-large-scale integration,Floorplan | Conference |
Volume | ISSN | ISBN |
1 | 0277-674X | 0-7803-2570-2 |
Citations | PageRank | References |
0 | 0.34 | 12 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Abdelhakim Safir | 1 | 0 | 0.34 |
| Baher Haroun | 2 | 34 | 9.20 |
| Krishnaiyan Thulasiraman | 3 | 255 | 25.49 |