Name
Abstract | ||
|---|---|---|
Large-scale hardware logic emulation using software configurable hardware provides a new means to significantly improve verification of complex integrated circuits such as today's advanced microprocessors. The essence of hardware logic emulation is the provision of a hardware prototype of the circuit being designed. Such a hardware prototype can execute both pseudo-random verification vectors and software application programs up to six orders-of-magnitude faster than conventional software logic simulators. Trillions of verification vectors can be run on the emulation model for verification in only a few weeks compared to the prior best practice of running only billions of verification vectors in many months. Application of hardware logic emulation requires a sound design methodology with an HDL model (RTL or at least gate-level), an unlimited source of vectors or software applications intended to exercise the design in a target system. |
Year | DOI | Venue |
|---|---|---|
1995 | 10.1109/ICCD.1995.528804 | Austin, TX |
Keywords | Field | DocType |
circuit analysis computing,digital simulation,formal verification,hardware description languages,logic CAD,microprocessor chips,reconfigurable architectures,HDL,Motorola 68060,RTL,circuit verification,configurable hardware,emulation verification,gate-level,hardware description language,hardware logic emulation,microprocessors,pseudo-random verification vectors,software application programs | Functional verification,Intelligent verification,Computer science,Parallel computing,Semulation,Emulation,High-level verification,Software verification,Hardware emulation,Embedded system,Hardware description language | Conference |
ISSN | ISBN | Citations |
1063-6404 | 0-8186-7165-3 | 14 |
PageRank | References | Authors |
2.33 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jainendra Kumar | 1 | 14 | 2.33 |
| Noel R. Strader | 2 | 14 | 2.33 |
| Jeff Freeman | 3 | 14 | 2.33 |
| Michael Miller | 4 | 14 | 2.33 |