Name
Title | ||
|---|---|---|
Synthesis and retiming for the pseudo-exhaustive BIST of synchronous sequential circuits |
Abstract | ||
|---|---|---|
In this work, we present a new approach for the pseudo-exhaustive BIST of synchronous sequential circuits. We first give a characterization of the flip-flops that cause the unbalanced structure of the acyclic circuit using peripheral retiming techniques, and, consequently, both logic optimization and balancing problem are considered and solved in the same phase. Second, the balancing solution is considered as a first step of the partitioning problem. For the remaining balanced circuit, the segmentation edges are selected such that there is a retiming minimizing the number of segmentation cells in the retimed circuit. Experimental results show that our approach significantly reduces the hardware overhead relative to the existing approaches |
Year | DOI | Venue |
|---|---|---|
1995 | 10.1109/TEST.1995.529898 | Washington, DC |
Keywords | Field | DocType |
automatic testing,boundary scan testing,built-in self test,fault diagnosis,flip-flops,logic partitioning,logic testing,minimisation of switching nets,sequential circuits,timing,acyclic circuit,balancing problem,flip-flops,hardware overhead reduction,logic optimization,number of segmentation cells,partitioning problem,peripheral retiming techniques,pseudo-exhaustive BIST,segmentation edges,synchronous sequential circuits,synthesis,unbalanced structure | Retiming,Sequential logic,Computer science,Segmentation,Logic optimization,Balanced circuit,Parallel computing,Automatic testing,Combinational logic,Electronic engineering,Real-time computing,Built-in self-test | Conference |
ISSN | ISBN | Citations |
1089-3539 | 0-7803-2992-9 | 0 |
PageRank | References | Authors |
0.34 | 10 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Samir Lejmi | 1 | 0 | 0.34 |
| Bozena Kaminska | 2 | 1155 | 189.76 |
| Bechir Ayari | 3 | 0 | 0.34 |