Name
Abstract | ||
|---|---|---|
The last fifteen years have witnessed a resurgence of interest in asynchronous digital design techniques as they promise to liberate VLSI systems from clock skew problems, offer the potential for low power and high performance and encourage a modular design philosophy which makes incremental technological migration a much easier task. This activity has revealed a need for modelling and simulation techniques suitable for the asynchronous design style. The concurrent process algebra communication sequential processes (CSP) is increasingly advocated as particularly suitable for this purpose. This paper discusses the modelling of SAMIPS, a synthesisable asynchronous MIPS processor core, in Balsa, a CSP-based, asynchronous hardware description language and synthesis tool. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/SIMSYM.2004.1299484 | Annual Simulation Symposium |
Keywords | Field | DocType |
VLSI,asynchronous circuits,communicating sequential processes,hardware description languages,high level synthesis,microprocessor chips,semiconductor device models,Balsa,SAMIPS modelling,VLSI systems,asynchronous design,asynchronous digital design techniques,asynchronous hardware description language,communication sequential processes,concurrent process algebra,hardware synthesis tool,high performance design,low power design,modular design philosophy,synthesisable asynchronous MIPS processor core | Logic synthesis,Asynchronous communication,Computer science,Communicating sequential processes,High-level synthesis,Real-time computing,Clock skew,Modular design,Multi-core processor,Hardware description language | Conference |
ISSN | ISBN | Citations |
1080-241X | 0-7695-2110-X | 6 |
PageRank | References | Authors |
0.59 | 14 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zhang, Q. | 1 | 6 | 0.59 |
| Theodoropoulos, G. | 2 | 110 | 8.22 |