Name
Abstract | ||
|---|---|---|
Abstract - This paper,presents,a new,optimization technique called architectural retiming which is able to im- prove the performance,of many,latency-constrained circuits. Architectural retiming achieves this by increasing the num- ber of registers on the latency-constrained,path while pre- serving the functionality and latency of the circuit. This is done using the concept of a negative register, which can be implemented,using precomputation,and prediction. We use the name,architectural retiming since it both resched- ules operations,in time and,modifies,the structure of the circuit to preserve its functionality. We illustrate the use of architectural retiming on two realistic examples,and present performance,improvement,results for a number,of sample circuits. 1 The Problem The performance,of synchronous,digital systems is measured |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1109/DAC.1996.545665 | Las Vegas, NV |
Keywords | Field | DocType |
circuit CAD,high level synthesis,logic CAD,pipeline processing,architectural retiming,latency-constrained circuits,negative register,optimization,pipelining,precomputation,sample circuits | Retiming,Pipeline (computing),Computer architecture,Precomputation,Computer science,Latency (engineering),Parallel computing,Real-time computing,Electronic circuit,Performance improvement | Conference |
ISSN | ISBN | Citations |
0738-100X | 0-7803-3294-6 | 31 |
PageRank | References | Authors |
2.20 | 7 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Soha Hassoun | 1 | 535 | 241.27 |
| Carl Ebeling | 2 | 1405 | 185.32 |