Name
Abstract | ||
|---|---|---|
This paper presents a new standard-cells based low-power subnanosecond 64-bit adder. For the first time, in the proposed circuit, a hybrid quaternary carry-look-ahead carry-skip tree is exploited to quickly compute carries into appropriate positions. Moreover, sum units organized as carry-increment blocks are used. When realized with the standard-cell libraries of the ST 0.18 μm 1.8 V CMOS technology, the new adder exhibits a computational delay of just 980 ps, an average power dissipation of 27 mW at 500 MHz and a silicon area occupancy of about 0.015 mm2. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1109/ICECS.2003.1302035 | Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference |
Keywords | DocType | Volume |
CMOS logic circuits,adders,carry logic,logic design,low-power electronics,0.18 micron,1.8 V,27 mW,500 MHz,64 bit,980 ps,CMOS technology,carry-increment block sum units,carry-look-ahead,computational delay,hybrid quaternary carry-skip tree,low-power adder,standard-cells based adder,subnanosecond adder | Conference | 1 |
ISBN | Citations | PageRank |
0-7803-8163-7 | 4 | 0.45 |
References | Authors | |
5 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Stefania Perri | 1 | 41 | 2.91 |
| Pasquale Corsonello | 2 | 4 | 0.45 |
| Giovanni Staino | 3 | 4 | 0.45 |