Name
Abstract | ||
|---|---|---|
The general objective of our work is to develop methods to reduce the power consumption of arithmetic modules, while maintaining the delay unchanged and keeping the increase in the area to a minimum. Here we illustrate some techniques for a radix-4 divider realized in 0.6 μm CMOS technology. Using techniques such as switching-off not active blocks, retiming the recurrence, equalizing the paths to reduce glitches, using gates with lower drive capability, and changing the redundant representation, we obtained a power consumption reduction of 35% with respect to the standard implementation. The techniques used here should be applicable to a variety of arithmetic modules which have similar characteristics |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1109/LPE.1996.547508 | Monterey, CA |
Keywords | Field | DocType |
cmos logic circuits,digital arithmetic,dividing circuits,integrated circuit design,logic design,timing,0.6 micron,cmos technology,arithmetic modules,low-power radix-4 divider,power consumption reduction,arithmetic,maintenance engineering,energy dissipation,power dissipation,adders | Logic synthesis,Retiming,Glitch,Adder,Computer science,Radix,Electronic engineering,CMOS,Integrated circuit design,Energy consumption | Conference |
ISBN | Citations | PageRank |
0-7803-3571-6 | 1 | 0.46 |
References | Authors | |
1 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Nannarelli, A. | 1 | 1 | 0.46 |
| Lang, T. | 2 | 1 | 0.46 |