Name
Abstract | ||
|---|---|---|
This paper presents a new effective scheme to decompress in parallel deterministic test patterns for circuits with multiple scan chains. Two implementations of the scheme are discussed. In the first one, the patterns are generated by the reseeding of a hardware structure which is mostly comprised of the already existing DFT environment. In the second approach, the patterns are generated through the execution of a program on a simple embedded processor. Extensive experiments with the largest ISCAS'89 benchmarks show that the proposed technique greatly reduces the amount of test data with low cost. Efficient automatic test pattern generation algorithms are also presented to enhance the efficiency of the proposed approach |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1109/TEST.1996.556961 | Washington, DC |
Keywords | Field | DocType |
automatic testing,boundary scan testing,built-in self test,data compression,integrated circuit testing,logic testing,2D test data decompressor,ATPG algorithms,automatic test pattern generation,concatenation technique,deterministic test patterns,dynamic compaction algorithm,embedded processor,hardware structure reseeding,multiple scan designs,test data reduction,variable-length seeds | Graphics,Automatic test pattern generation,Polynomial,Computer science,Parallel computing,Electronic engineering,Test data,Electronic circuit,Test compression,Data compression,Built-in self-test | Conference |
ISSN | ISBN | Citations |
1089-3539 | 0-7803-3541-4 | 24 |
PageRank | References | Authors |
3.27 | 9 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Nadime Zacharia | 1 | 24 | 3.27 |
| Janusz Rajski | 2 | 69 | 9.75 |
| Jerzy Tyszer | 3 | 24 | 3.27 |
| Waicukauski, J.A. | 4 | 447 | 50.41 |