Paper Info
Title
Multiway partitioner for high performance FPGA based board architectures
Abstract
Field-programmable gate array based board architectures are becoming fairly common for rapid prototyping and custom computing. In order to map large designs on multiple FPGA based boards, the design has to be partitioned into two or more segments. In this paper we describe the architecture, constraints, and a solution to the area and pin constrained partitioning problem. Our effort is directed towards partitioning “huge” designs in relatively small amount of time, thus giving the designer a capability to explore many mapping solutions. The board level architecture is based on multi-chip modules, where each MCM consists of three Xilinz 4025 FPGAs and a dual ported one mega byte SRAM. In its smallest configuration the board can map 300,000 gate size designs
Year
DOI
Venue
1996
10.1109/ICCD.1996.563609
Austin, TX
Keywords
Field
DocType
circuit layout CAD,computer architecture,field programmable gate arrays,multichip modules,software prototyping,Xilinz 4025 FPGAs,board level architecture,dual ported one mega byte SRAM,high performance FPGA based board architectures,multi-chip modules,multiway partitioner,pin constrained partitioning problem,rapid prototyping
Rapid prototyping,Byte,Computer architecture,Computer science,Parallel computing,Software prototyping,Field-programmable gate array,Gate array,Electronic design automation,Process design,Porting,Embedded system
Conference
ISSN
ISBN
Citations 
1063-6404
0-8186-7554-3
2
PageRank 
References 
Authors
0.84
4
2
Name
Order
Citations
PageRank
Vijayanand Sankarasubramanian120.84
Dinesh Bhatia232.55