Name
Abstract | ||
|---|---|---|
This paper describes the parallelization of a diagnostic fault simulator for stuck-at faults in sequential circuits. The parallelization is performed by partitioning the diagnostic equivalence classes obtained by simulating the first few test vectors of the test set. The partitions are then simulated in parallel, independent of each other for the remaining vectors. Thus there is no communication overhead. Results on performance speedup and diagnostic resolution loss are provided for the ISCAS 89 benchmark circuits. |
Year | DOI | Venue |
|---|---|---|
1997 | 10.1109/ICVD.1997.568157 | VLSI Design |
Keywords | Field | DocType |
circuit analysis computing,fault diagnosis,integrated circuit testing,integrated logic circuits,logic testing,parallel algorithms,sequential circuits,distributed diagnostic simulation,parallelization,partitioning strategy,sequential circuits,stuck-at faults | Stuck-at fault,Sequential logic,Computer science,Parallel algorithm,Parallel computing,Real-time computing,Equivalence class,Fault Simulator,Asynchronous circuit,Test set,Speedup | Conference |
ISSN | ISBN | Citations |
1063-9667 | 0-8186-7755-4 | 10 |
PageRank | References | Authors |
0.74 | 8 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Venkataraman, S. | 1 | 10 | 0.74 |
| W. Kent Fuchs | 2 | 1469 | 279.02 |