Name
Abstract | ||
|---|---|---|
We present a new pseudo-differential comparator block that behaves like a comparator array, but has a reduced area, power consumption, and input capacitance. By combining two of the new comparator blocks with input sample and hold circuits, in an interleaving architecture, and by using a Wallace-tree encoder, it is possible to obtain an ADC with limited resolution (up to 6 bits), but with very low power consumption, and also with low area and low supply voltage. As an example, we have designed 4-bit ADC as a coarse converter in a 13 bit pipeline ADC. . It is implemented in a 0.35μm CMOS technology, has 0.034mm2 and has power consumption of 210 μW, with an estimated input capacitance of 11 fF. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/ISCAS.2004.1328380 | Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium |
Keywords | Field | DocType |
CMOS integrated circuits,analogue-digital conversion,comparators (circuits),low-power electronics,sample and hold circuits,0.35 micron,11 fF,210 muW,CMOS parallel A/D converter,CMOS technology,Wallace-tree encoder,comparator array,embedded applications,input capacitance,interleaving architecture,low power consumption,pseudo-differential comparator block,sample and hold circuits,supply voltage | Comparator,Capacitance,Computer science,Electronic engineering,CMOS,Encoder,Sample and hold,Electronic circuit,Electrical engineering,Interleaving,Low-power electronics | Conference |
Volume | ISBN | Citations |
1 | 0-7803-8251-X | 0 |
PageRank | References | Authors |
0.34 | 2 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jorge R. Fernandes | 1 | 154 | 34.16 |
| Manuel M. Silva | 2 | 46 | 9.80 |