Name
Abstract | ||
|---|---|---|
The high complexity of circuits which currently consist of several millions of transistors, can only be managed using a concise design flow. Recently, the One-Pass Synthesis paradigm came up, i.e. to consider the whole design process as one flow instead of isolated steps. In this context, designing circuits based on the mapping of Binary Decision Diagrams (BDDs) shows several advantages. While various BDD based approaches for logic minimization or design for testability have been proposed, in this paper we show that placement and routing of BDD circuits can be optimized at a high level of abstraction. Based on algorithms for reducing the number of nodes and edge crossings, we demonstrate on multiple benchmarks that significant improvements are possible in reason- able time. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/ISCAS.2004.1329504 | Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium |
Keywords | Field | DocType |
binary decision diagrams,circuit complexity,circuit optimisation,design for testability,logic design,BDD circuits,abstraction level,binary decision diagrams,circuits complexity,design flow,design for testability,design process,logic minimization,one-pass synthesis paradigm,placement optimization,routing optimization,transistors | Logic synthesis,Design for testing,Logic gate,Circuit complexity,Computer science,Binary decision diagram,Design flow,Electronic engineering,Process design,Design process | Conference |
Volume | ISBN | Citations |
5 | 0-7803-8251-X | 0 |
PageRank | References | Authors |
0.34 | 12 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Thomas Eschbach | 1 | 33 | 4.00 |
| Rolf Dreschler | 2 | 0 | 0.34 |
| Bernd Becker | 3 | 855 | 73.74 |