Name
Abstract | ||
|---|---|---|
This paper presents a technique for reducing leakage power of the circuits employing a clock gating scheme on Partially Depleted Silicon On Insulator (PD-SOI). To reduce leakage power while a local clock is disabled, Vth of each transistor is dynamically controlled by body biasing corresponding to the mode of the local clock. Using PD-SOI is the key to control Vth within one clock cycle by forward biasing, where Vth without biasing is designed higher than usual to reduce leakage power. The SPICE simulation results have shown that the proposed technique reduces leakage power by 82% with small area penalty. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/ISCAS.2004.1329346 | Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium |
Keywords | Field | DocType |
MOSFET,SPICE,leakage currents,semiconductor device models,silicon-on-insulator,SOI,SPICE simulation,Si,body biasing,clock gating scheme,forward biasing,leakage power reduction,partially depleted silicon on insulator | Silicon on insulator,Clock gating,Spice,Computer science,Voltage,Electronic engineering,Cycles per instruction,MOSFET,Transistor,Electrical engineering,Biasing | Conference |
Volume | ISBN | Citations |
2 | 0-7803-8251-X | 3 |
PageRank | References | Authors |
0.42 | 1 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Fukuoka, K. | 1 | 3 | 0.42 |
| Masaaki Iijima | 2 | 13 | 4.68 |
| Hamada, K. | 3 | 4 | 1.45 |
| Numa, M. | 4 | 37 | 3.92 |