Name
Abstract | ||
|---|---|---|
IPSec is a suite of protocols that adds security to communications at the IP level. Protocols within the IPSec suite make extensive use of cryptographic algorithms. Since these algorithms are computationally very intensive, some hardware acceleration is needed to support high throughput. In this paper we discuss a scheduling algorithm for distributing IPSec packet processing over the CPU with a software implementation of the cryptographic algorithms considered and multiple cryptographic accelerators. High-level simulations and the related results are provided to show the properties of the algorithm. Some architectural improvements suitable to better exploit this scheduling algorithm are also presented. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/ASAP.2004.1342487 | ASAP |
Keywords | Field | DocType |
computer networks,cryptography,packet switching,processor scheduling,telecommunication security,transport protocols,IP level,IPSec multi-accelerator based systems,IPSec packet processing,IPSec suite,communications security,cryptographic accelerators,cryptographic algorithms,hardware acceleration,high-level simulations,packet scheduling algorithm,protocols | IPsec,Fair-share scheduling,Security Parameter Index,Computer science,Scheduling (computing),Parallel computing,Real-time computing,Cryptographic primitive,Packet processing,Hardware acceleration,Round-robin scheduling | Conference |
ISSN | ISBN | Citations |
2160-0511 | 0-7695-2226-2 | 5 |
PageRank | References | Authors |
0.57 | 5 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Fabien Castanier | 1 | 5 | 0.57 |
| Alberto Ferrante | 2 | 78 | 13.68 |
| Vincenzo Piuri | 3 | 859 | 100.65 |