Name
Abstract | ||
|---|---|---|
Circuit designers can efficiently verify designs at the bit and word levels in one graph-based data structure. The authors present the representation technique, manipulation algorithms for K*BMDs, and experimental results other data structures |
Year | DOI | Venue |
|---|---|---|
1997 | 10.1109/54.587742 | Design & Test of Computers, IEEE |
Keywords | Field | DocType |
Boolean functions,data structures,formal verification,integrated circuit design,logic CAD,logic testing,K*BMD,bit level,circuit design,graph-based data structure,manipulation algorithms,verification data structure,word level | Data structure,Boolean circuit,Computer science,Logic optimization,Circuit extraction,Algorithm,Physical design,High-level verification,Circuit minimization for Boolean functions,And-inverter graph | Journal |
Volume | Issue | ISSN |
14 | 2 | 0740-7475 |
Citations | PageRank | References |
31 | 1.74 | 13 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Rolf Drechsler | 1 | 3707 | 351.36 |
| B. Becker | 2 | 411 | 36.80 |
| Stefan Ruppertz | 3 | 76 | 3.81 |