Name
Abstract | ||
|---|---|---|
The problem of the design of a highly testable 1-out-of-3 CMOS checker has been considered. First some recently presented CMOS checkers have been analyzed, then a novel checker has been proposed to be certainly preferable from the self-testing capability and overall performance point of view |
Year | DOI | Venue |
|---|---|---|
1993 | 10.1109/DFTVS.1993.595823 | Venice |
Keywords | Field | DocType |
CMOS logic circuits,1-out-of-3 CMOS checker,bridging faults,performance,self-testing | Cmos logic circuits,System testing,Computer science,Logic testing,CMOS,Electronic engineering,Real-time computing,Built-in self-test | Conference |
ISSN | ISBN | Citations |
1550-5774 | 0-8186-3502-9 | 6 |
PageRank | References | Authors |
0.58 | 7 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Cecilia Metra | 1 | 710 | 75.41 |
| M. Favalli | 2 | 295 | 42.09 |
| P. Olivo | 3 | 342 | 58.07 |
| B. Ricco | 4 | 136 | 24.67 |