Paper Info
Title
Performance analysis of parallel frame synchronization scheme in SDH systems
Abstract
We analyze the performance of a new parallel frame synchronization system used for SDH networks. The performance is measured by using false synchronous probability P/sub FS/, the average synchronous incoming time T/sub ASI/, the average synchronous catching time T/sub ASC/, and the average synchronization holding time T/sub ASH/. Analysis indicates that the performance of our scheme is similar to that of the traditional approaches, or better under some condition. Furthermore, our scheme permits designers to use off-the-shelf integrated circuits to build SDH synchronization system.
Year
DOI
Venue
1997
10.1109/ICCCN.1997.623351
Las Vegas, NV
Keywords
Field
DocType
cache storage,probability,synchronisation,synchronous digital hierarchy,SDH networks,SDH synchronization system,average synchronization holding time,average synchronous catching time,average synchronous incoming time,false synchronous probability,off-the-shelf integrated circuits,parallel frame synchronization,performance analysis
Synchronization,Computer science,Frame synchronization,Computer network,Holding time,Real-time computing,Electronic circuit,Integrated circuit,Detector,Leak detection,Payload,Distributed computing
Conference
ISSN
ISBN
Citations 
1095-2055
0-8186-8186-1
0
PageRank 
References 
Authors
0.34
2
2
Name
Order
Citations
PageRank
Obaidat, M.S.129039.97
Teng, J.200.34