Paper Info
Title
A way memoization technique for reducing power consumption of caches in application specific integrated processors
Abstract
This paper presents a technique for eliminating redundant cache-tag and cache-way accesses to reduce power consumption. The basic idea is to keep a small number of most recently used (MRU) addresses in a memory address buffer (MAB) and to omit redundant tag and way accesses when there is a MAB-hit. Since the approach keeps only tag and set-index values in the MAB, the energy and area overheads are relatively small even for a MAB with a large number of entries. Furthermore, the approach does not sacrifice the performance. In other words, neither the cycle time nor the number of executed cycles increases. The proposed technique has been applied to the Fujitsu VLIW processor (FR-V) and its power saving has been estimated using NanoSim. Experiments for 32 kB 2-way set associative caches show the power consumption of I-cache and D-cache can be reduced by 40% and 50%, respectively.
Year
DOI
Venue
2005
10.1109/DATE.2005.45
Clinical Orthopaedics and Related Research
Keywords
DocType
ISSN
application specific integrated circuits,cache storage,low-power electronics,microprocessor chips,power consumption,2-way set associative caches,d-cache,fr-v,fujitsu vliw processor,i-cache,mab-hit,nanosim,cache-way accesses,memory address buffer,most recently used addresses,reduced power consumption,redundant cache-tag accesses,set-index values,way memoization,indexation,hardware architecture,cycle time
Conference
1530-1591
ISBN
Citations 
PageRank 
0-7695-2288-2
8
0.55
References 
Authors
12
2
Name
Order
Citations
PageRank
Tohru Ishihara171987.96
Farzan Fallah255743.73