Name
Abstract | ||
|---|---|---|
As the sizes of general and special purpose processors increase rapidly, generating high quality manufacturing tests for them is becoming a serious problem in industry. This paper describes a novel method for hierarchical functional test generation for processors which targets one embedded module at a time and uses commercial ATPG tools to derive tests for faults within the module. Applying the technique to benchmark processor designs, we were able to obtain test efficiencies for the embedded modules of the processors which were extremely close to what the commercial ATPG could do with complete access to the module. The hierarchical approach used produced this result, using the same commercial tool, but required a CPU time several orders of magnitude less than when using a conventional, flat view of the circuit |
Year | DOI | Venue |
|---|---|---|
1997 | 10.1109/TEST.1997.639687 | Washington, DC |
Keywords | Field | DocType |
automatic testing,integrated circuit testing,logic testing,microprocessor chips,production testing,ATPG tools,benchmark processor designs,commercial ATPG,embedded module,functional test generation method,general purpose processors,hierarchical functional test generation,manufacturing tests,special purpose processors,test efficiencies | Automatic test pattern generation,Logic testing,Production testing,CPU time,Fault detection and isolation,Computer science,Automatic testing,Real-time computing,Process design,Benchmark (computing) | Conference |
ISSN | ISBN | Citations |
1089-3539 | 0-7803-4209-7 | 53 |
PageRank | References | Authors |
3.78 | 9 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Raghuram S. Tupuri | 1 | 114 | 10.63 |
| J. Abraham | 2 | 4905 | 608.16 |