Name
Abstract | ||
|---|---|---|
This paper proposes applying a logic synthesis approach to high level synthesis from SpecC specifications to timed asynchronous gate-level circuits. The state-based logic synthesis is used to allow for global and timing optimization. In order to reduce the overhead in resetting phases, a protocol called early acknowledgment protocol and its STG (signal transition graph) generation technique are proposed. In this protocol, the state variables inserted to guarantee that STGs have CSC (complete state coding) usually cause no overhead. The experiments to synthesize a portion of a DCT circuit show that the proposed method can handle a nontrivial example and produce a smaller and faster circuit than a previous approach. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/ASYNC.2005.22 | ASYNC |
Keywords | DocType | ISSN |
petri nets,asynchronous circuits,circuit optimisation,discrete cosine transforms,high level synthesis,specification languages,state-space methods,timing,csc,dct circuit,stg generation,specc specifications,asynchronous gate-level circuits,complete state coding,early acknowledgment protocol,global optimization,resetting phase overhead,resource allocation/scheduling,signal transition graph,state-based logic synthesis,timed asynchronous circuits,timing optimization,balsa,specc,logic synthesis,timed stgs,col,asynchronous circuit | Conference | 1522-8681 |
ISBN | Citations | PageRank |
0-7695-2305-6 | 9 | 0.58 |
References | Authors | |
12 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tomohiro Yoneda | 1 | 353 | 41.62 |
| Atsushi Matsumoto | 2 | 9 | 0.58 |
| Manabu Kato | 3 | 9 | 0.58 |
| Chris J. Myers | 4 | 607 | 75.73 |