Name
Title | ||
|---|---|---|
Design of a flexible VLSI architecture for M-channel filter bank lifting factorizations |
Abstract | ||
|---|---|---|
We present an efficient VLSI architecture focusing on M-channel multirate filter banks using the lifting scheme. Since the M-channel lifting factorization results in a signal flow graph with a variable structure, the architecture must have a high degree of flexibility to allow the implementation of basically different lifting factorizations. The proposed architecture is convenient to realize arbitrary lifting factorizations on a variable amount of arithmetic resources, leading to an adaptability for the real-time requirements of various DSP applications. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/ICASSP.2005.1416254 | ICASSP '05). IEEE International Conference |
Keywords | Field | DocType |
VLSI,channel bank filters,computational complexity,digital arithmetic,field programmable gate arrays,integrated circuit design,logic design,signal flow graphs,DSP applications,FPGA implementation,M-channel filter bank lifting factorizations,arithmetic resources,computational complexity,flexible VLSI architecture design,multirate filter banks,signal flow graph | Logic synthesis,Digital signal processing,Lifting scheme,Computer science,Filter bank,Parallel computing,Field-programmable gate array,Very-large-scale integration,Signal-flow graph,Computational complexity theory | Conference |
Volume | ISSN | ISBN |
5 | 1520-6149 | 0-7803-8874-7 |
Citations | PageRank | References |
1 | 0.36 | 4 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ruben Bartholomä | 1 | 1 | 0.36 |
| Thomas Greiner | 2 | 13 | 6.84 |
| Frank Kesel | 3 | 1 | 0.36 |