Name
Abstract | ||
|---|---|---|
A VLSI implementation of the H.324 audiovisual codec is described. A number of sophisticated low-power architectures have been devised dedicatedly for the mobile use. A set of specific functional units, each corresponding to a process of H.263 video codec, is employed to lighten different performance bottlenecks. A compact DSP core composed of two MAC units is used for both ACELP and MP-MLQ coding schemes of the G.723.1 speech codec. The proposed audiovisual codec core has been implemented by using 0.35 μm CMOS 4LM technology, which contains totally 420 K transistors with the dissipation of 224.32 mW from single 3.3 V supply |
Year | DOI | Venue |
|---|---|---|
1998 | 10.1109/ASPDAC.1998.669566 | Yokohama |
Keywords | Field | DocType |
CMOS integrated circuits,VLSI,encoding,maximum likelihood decoding,speech codecs,video codecs,ACELP,CMOS 4LM technology,DSP core,G.723.1 speech codec,H.324 audiovisual codec,MAC units,MP-MLQ coding,VLSI implementation,functional units,low-power implementation,mobile computing,video codec | Mobile computing,Digital signal processing,Speech coding,Computer science,Adaptive Multi-Rate audio codec,Electronic engineering,Real-time computing,Enhanced Variable Rate Codec,Algebraic code-excited linear prediction,Very-large-scale integration,Codec | Conference |
ISBN | Citations | PageRank |
0-7803-4425-1 | 1 | 0.36 |
References | Authors | |
5 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| T. Onoye | 1 | 37 | 10.36 |
| Fujita, G. | 2 | 8 | 1.35 |
| Okuhata, H. | 3 | 1 | 0.36 |
| Miki, M.H. | 4 | 1 | 0.36 |