Name
Abstract | ||
|---|---|---|
Recently a mathematical framework was presented that bridges the gap between bit level BDD representation and word level representations such as BMD and TED. Here we present an approach that demonstrates that these diagrams admit fast evaluation of circuits for multiple outputs. The representation is based on characteristic function which provides faster evaluation time as well as compact representation. The average path length is used as a metric for evaluation time. The results obtained for benchmark circuits shows lesser number of nodes and faster evaluation time compared to binary representation. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/HLDVT.2004.1431237 | HLDVT |
Keywords | Field | DocType |
Boolean functions,binary decision diagrams,logic circuits,logic simulation,logic testing,CF,MODD,benchmark circuit,binary representation,bit level BDD representation,characteristic function,mathematical framework,multiple-output function,path length,word level representation | Boolean function,Average path length,Digital electronics,Boolean circuit,Logic optimization,Computer science,Algorithm,Theoretical computer science,Logic simulation,And-inverter graph,Binary number | Conference |
ISSN | ISBN | Citations |
1552-6674 | 0-7803-8714-7 | 4 |
PageRank | References | Authors |
0.48 | 10 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| T. L. Rajaprabhu | 1 | 9 | 1.97 |
| A. Singh | 2 | 42 | 8.59 |
| A. M. Jabir | 3 | 35 | 5.73 |
| Dhiraj K. Pradhan | 4 | 2670 | 452.20 |