Name
Title | ||
|---|---|---|
Feedforward-type parasitic capacitance canceler and its application to 4 Gb/s T/H circuit |
Abstract | ||
|---|---|---|
This paper proposes a novel parasitic capacitance cancellation method. Since parasitics are canceled by feedforwarding signals, a circuit using the proposed cancellation method is always stable unlike a conventional method using a negative impedance converter. This cancellation method is applicable to a balanced-type circuit driving capacitors with source followers. As an example it is applied to implementation of a high-speed track-and-hold circuit (T/H circuit). Thanks to this method implementation of a 4-Gbit/s T/H circuit with 6-bit accuracy is confirmed through HSPICE simulations with 90-nm CMOS process under 0.9-V power supply voltage. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/ISCAS.2005.1465897 | ISCAS (6) |
Keywords | Field | DocType |
CMOS analogue integrated circuits,capacitance,circuit stability,feedforward,sample and hold circuits,0.9 V,4 Gbit/s,6 bit,90 nm,CMOS process,balanced-type circuit,circuit stability,feedforward-type parasitic capacitance canceler,high-speed T/H circuit,source followers,track-and-hold circuit | Negative impedance converter,Parasitic capacitance,Capacitance,Capacitor,Computer science,Voltage,Electrical impedance,Electronic engineering,Parasitic extraction,Electrical engineering,Equivalent circuit | Conference |
ISSN | ISBN | Citations |
0271-4302 | 0-7803-8834-8 | 0 |
PageRank | References | Authors |
0.34 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| T. Sato | 1 | 91 | 16.41 |
| Shinichi Takagi | 2 | 3 | 9.69 |
| Fujii, M. | 3 | 1 | 1.04 |
| Yuki Hashimoto | 4 | 168 | 27.29 |