Paper Info
Title
A 60 ns 500×12 0.35 μm CMOS low-power scanning read-out IC for cryogenic infra-red sensors
Abstract
The paper proposes a low-cost scanning read-out IC architecture for large arrays of infra-red photon sensors operating at cryogenic temperatures. The low-power and compact 50×100 μm2 active pixel sensor area is achieved by the use of novel CMOS basic building blocks for single-capacitor integration and correlated double sampling, embedded pixel-test, pixel charge-multiplexing, video multiplexing and offset calibration. As a result, a low-cost 500×12 and 60 ns/pixel system-on-chip realization, capable of capturing high-resolution and real-time infra-red images, such as 640×500 @ 100 fps or 2560×500 @ 25 fps, is presented for a standard 0.35 μm CMOS technology.
Year
DOI
Venue
2005
10.1109/ISCAS.2005.1464944
international symposium on circuits and systems
Keywords
DocType
ISSN
cmos image sensors,built-in self test,cryogenic electronics,infrared detectors,infrared imaging,integrated circuit design,integrating circuits,low-power electronics,multiplexing,optical arrays,signal sampling,system-on-chip,video signal processing,0.35 micron,100 micron,50 micron,60 ns,cmos ic,cmos low-power scanning read-out ic,active pixel sensor area,correlated double sampling,cryogenic infra-red sensor arrays,embedded pixel-test,high-resolution infra-red images,low-power ic,offset calibration,pixel charge-multiplexing,real-time infra-red images,single-capacitor integration,video multiplexing,low power electronics,high resolution,photonic integrated circuits,cryogenics,active pixel sensor,system on chip,cmos technology,cmos integrated circuits,infra red,real time
Conference
0271-4302
ISBN
Citations 
PageRank 
0-7803-8834-8
0
0.34
References 
Authors
1
5
Name
Order
Citations
PageRank
francisco serragraells161.92
Bertrand Misischi200.34
eduardo casanueva300.34
César Méndez400.34
Lluis Teres5172.09