Paper Info
Title
Energy optimization of tapered buffers for CMOS on-chip switching power converters
Abstract
This work presents a model to determine the power consumption of tapered buffers, validating its results with transistor-level simulations. Focusing on their application as gate drivers for high-frequency on-chip switching power converters, the need for a fall-rise time evaluation at the output of the tapered buffer is discussed. Consequently, the output fall-rise time is modeled and validated by means of simulations. Given the linear relation between the fall-rise time and the switching losses of the power MOSFET, an optimized design procedure is proposed to concurrently minimize the switching losses of the tapered buffer together with the power MOSFET switching losses. The work concludes with a design example for a 15000 μm-width PMOS transistor, presenting an optimum tapering factor of 21, for a specific 0.35 μm standard CMOS technology.
Year
DOI
Venue
2005
10.1109/ISCAS.2005.1465620
ISCAS (5)
Keywords
Field
DocType
CMOS integrated circuits,DC-DC power convertors,buffer circuits,power MOSFET,switching convertors,0.35 micron,15000 micron,CMOS,PMOS transistor,converter gate drivers,driver output fall-rise time,on-chip switching power converters,power MOSFET switching losses,tapered buffer energy optimization,tapering factor
Propagation delay,Computer science,Power semiconductor device,Power MOSFET,CMOS,Converters,Electronic engineering,PMOS logic,Transistor,Energy consumption,Electrical engineering
Conference
ISSN
ISBN
Citations 
0271-4302
0-7803-8834-8
6
PageRank 
References 
Authors
1.19
2
4
Name
Order
Citations
PageRank
Gerard Villar1267.10
Eduard Alarcón239164.43
J. Madrenas3102.45
Francesc Guinjoan48420.97