Title
An architecture of a matrix-vector multiplier dedicated to video decoding and three-dimensional computer graphics
Abstract
An architecture of a matrix-vector multiplier (MVM) is devised, which is dedicated to MPEG-4 natural/synthetic video decoding. The MVM can perform the matrix-vector multiplication both in the inverse discrete cosine transform (IDCT) and in the geometrical transformation of three-dimensional computer graphics (3-D CG); or, specifically, it can achieve the multiplication of a 4×4 matrix by a four-tuple vector necessary in the one-dimensional IDCT for eight pixels and in the geometrical transformation for a point in a 3-D space. This paper describes a new architecture of this MVM and also shows the implementation result of a functional module composed of four MVMs with the use of 440-k transistors, which can operate at 20 MHz or less
Year
DOI
Venue
1999
10.1109/76.752097
Circuits and Systems for Video Technology, IEEE Transactions
Keywords
Field
DocType
code standards,computer graphics,decoding,digital signal processing chips,discrete cosine transforms,inverse problems,matrix multiplication,multiplying circuits,telecommunication standards,transform coding,video coding,20 MHz,3D CG,3D computer graphics,3D space,IDCT,MPEG-4 natural/synthetic video decoding,four-tuple vector,functional module,geometrical transformation,inverse discrete cosine transform,matrix-vector multiplier architecture,pixels,three-dimensional computer graphics,transistors
Computer graphics (images),Computer science,Matrix (mathematics),Discrete cosine transform,Multiplier (economics),Computational science,Multiplication,Artificial intelligence,Computer graphics,Computer vision,Transform coding,Decoding methods,Matrix multiplication
Journal
Volume
Issue
ISSN
9
2
1051-8215
Citations 
PageRank 
References 
1
0.41
7
Authors
4
Name
Order
Citations
PageRank
Fujishima, H.110.41
Y. Takemoto210.75
T. Onoye33710.36
Isao Shirakawa422065.34