Name
Abstract | ||
|---|---|---|
This paper describes a simple algorithm for eliminating possible aggressor-victim net pairs for crosstalk analysis. This algorithm makes use of the observation that timing constraints in sequential circuits apply to crosstalk induced pulses. We show how this algorithm can be applied to a design to prune the candidate list for ATPG to detect crosstalk glitches that are introduced by manufacturing defects. |
Year | DOI | Venue |
|---|---|---|
1999 | 10.1109/VTEST.1999.766650 | Dana Point, CA |
Keywords | Field | DocType |
VLSI,automatic test pattern generation,crosstalk,integrated circuit testing,production testing,sequential circuits,timing,ATPG,VLSI,aggressor-victim net pairs,candidate list,crosstalk analysis,crosstalk glitches,manufacturing defects,sequential circuits,temporal constraints,timing constraints | Glitch,Automatic test pattern generation,Sequential logic,Computer science,Production testing,Crosstalk,Real-time computing,Electronic engineering,SIMPLE algorithm,Very-large-scale integration | Conference |
ISSN | ISBN | Citations |
1093-0167 | 0-7695-0146-X | 7 |
PageRank | References | Authors |
0.72 | 3 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Michael A. Margolese | 1 | 7 | 0.72 |
| F. Joel Ferguson | 2 | 7 | 0.72 |