Name
Abstract | ||
|---|---|---|
Current code coverage metrics used in high level VLSI design methodology are based on statement, branch, toggle and condition coverages of the HDL code obtained by simulating validation vectors. These measures allow the designer to find sections of the HDL code not executed during validation. Feedback from the code coverage analysis helps generate additional vectors to exercise previously unexercised functionality. In this paper, we explore the relationship between results of RTL code coverage and the gate level fault coverage. Based on the observations of this empirical study we propose a new and improved code coverage metric “Validation Vector Grade (VVG)”. The VVG-approach modifies code coverage metrics by adding the concepts of observability and arithmetic fault library. VVG is an improved validation metric, which can also be used for early testability analysis at the RT level. Results of the VVG-approach at RT level are shown to be good indicators of the structural fault coverage. Experiments on actual telecommunication VLSI chip designs show that the VVG reported at the RT level can predict the post-synthesis gate level fault coverage with an error margin less than 4%. Also, the improvements in VVG at the RT level due to high-level design changes or added vectors track improvements in gate level fault coverage |
Year | DOI | Venue |
|---|---|---|
1999 | 10.1109/VTEST.1999.766663 | Dana Point, CA |
Keywords | Field | DocType |
VLSI,digital integrated circuits,fault diagnosis,high level synthesis,integrated circuit design,integrated circuit testing,logic testing,observability,vectors,RT level,RTL code coverage,arithmetic fault library,code coverage analysis,code coverage metric,fault coverage predictor,gate level fault coverage,high level VLSI design methodology,observability,post-synthesis gate level fault coverage,telecommunication VLSI chip designs,testability analysis,validation metric,validation vector grade | Code coverage,Observability,Fault coverage,Computer science,High-level synthesis,Real-time computing,Electronic engineering,Integrated circuit design,Very-large-scale integration,Computer engineering,Modified condition/decision coverage,Margin of error | Conference |
ISSN | ISBN | Citations |
1093-0167 | 0-7695-0146-X | 28 |
PageRank | References | Authors |
2.13 | 14 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pradip A. Thaker | 1 | 28 | 2.13 |
| Vishwani D. Agrawal | 2 | 3502 | 470.06 |
| Mona E. Zaghloul | 3 | 73 | 19.65 |