Name
Abstract | ||
|---|---|---|
Designers use formal logic and a theorem prover to verify that a complex microarchitecture always implements its instruction set correctly. Hardware verification accounts for a considerable portion of the costs in the microprocessor design process. Traditionally, designers have verified microprocessor designs using simulation techniques that help find most design faults. However, simulation never guarantees the correct operation of the final product. Some design faults are very difficult to detect by simulation; they may slip through the verification process into manufactured chips, raising costs. We believe that verification costs can be reduced by the judicious application of formal methods, which should lower the overall costs of design. |
Year | DOI | Venue |
|---|---|---|
1999 | 10.1109/40.768503 | IEEE Micro |
DocType | Volume | Issue |
Journal | 19 | 3 |
ISSN | Citations | PageRank |
0272-1732 | 13 | 0.83 |
References | Authors | |
10 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Warren A. Hunt, Jr. | 1 | 520 | 59.18 |
| Jun Sawada | 2 | 325 | 21.16 |