Name
Title | ||
|---|---|---|
A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme |
Abstract | ||
|---|---|---|
A precise on-chip voltage generator for gigascale DRAM's with a negative word-line scheme is described. It combines a charge-pump regulator and a series-pass regulator, and it also includes a positive and negative offset voltage generator that uses a bandgap generator with a differential amplifier. The proposed circuit was experimentally evaluated with a test device fabricated using a 0.3-μm process. The simulation results show that the series-pass regulator suppresses the noise on a word-line low voltage (negative) to below 30 mV for the word-line transient and VBB bouncing. A dc-voltage error of less than 6% without trimming is confirmed for the positive and negative offset voltage generator through the test device. These results show that the described scheme can be used in future low-voltage gigascale DRAM's |
Year | DOI | Venue |
|---|---|---|
1999 | 10.1109/4.777106 | Solid-State Circuits, IEEE Journal of |
Keywords | DocType | Volume |
DRAM chips,low-power electronics,voltage regulators,0.3 micron,bandgap generator,charge-pump regulator,differential amplifier,low-voltage gigascale DRAM,negative word-line architecture,offset voltage generator,on-chip voltage generator,series-pass regulator | Journal | 34 |
Issue | ISSN | Citations |
8 | 0018-9200 | 15 |
PageRank | References | Authors |
3.14 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tanaka, H. | 1 | 15 | 3.14 |
| Aoki, M. | 2 | 25 | 6.79 |
| Sakata, T. | 3 | 18 | 4.26 |
| Kimura, S. | 4 | 16 | 3.62 |