Name
Abstract | ||
|---|---|---|
A decoder of (64,35) Reed-Muller subcode has been implemented, dedicatedly for high-speed satellite communication. The trellis-based recursive maximum likelihood decoding algorithm, which greatly reduces the computational costs of the conventional Viterbi algorithm, can be performed on a single chip by using 3-stage pipeline architecture of an add-compare-select (ACS) tree. By using 0.6 μm CMOS triple-metal technology, the (64,35) decoder integrates totally 160,023 gates into a 151.3 mm2 die and operates at 60 MHz. The 600 Mbps (64,40) decoding system required for satellite communication can be constructed by employing 32 proposed decoders in parallel |
Year | DOI | Venue |
|---|---|---|
1999 | 10.1109/ISCAS.1999.780069 | Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium |
Keywords | Field | DocType |
CMOS digital integrated circuits,Reed-Muller codes,VLSI,block codes,digital communication,digital signal processing chips,high-speed integrated circuits,linear codes,maximum likelihood decoding,parallel architectures,pipeline processing,satellite communication,trellis codes,(64,35) decoder,0.6 micron,60 MHz,600 Mbit/s,CMOS triple-metal technology,Reed-Muller subcode,add-compare-select tree,high-speed satellite communication,linear block codes,parallel connected decoders,recursive maximum likelihood decoder,three-stage pipeline architecture,trellis-based recursive ML decoding algorithm | Computer science,CMOS,Electronic engineering,Viterbi decoder,Soft-decision decoder,Decoding methods,Communications satellite,Very-large-scale integration,Viterbi algorithm,Phase-shift keying | Conference |
Volume | ISBN | Citations |
4 | 0-7803-5471-0 | 0 |
PageRank | References | Authors |
0.34 | 3 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Miki, M.H. | 1 | 0 | 0.34 |
| Taki, D. | 2 | 0 | 0.34 |
| Fujita, G. | 3 | 8 | 1.35 |
| T. Onoye | 4 | 37 | 10.36 |